Transistor having hard-mask layers

ABSTRACT

A method for fabricating a transistor including the following steps is provided. First, a gate electrode is formed on a substrate, and a gate insulating layer is formed on the substrate in sequence, wherein the gate insulating layer covers the substrate and the gate electrode. Next, a patterned channel layer and a hard-mask layer are formed on the gate insulating layer, wherein the patterned channel layer and the hard-mask layer are located above the gate electrode, and the hard-mask layer is disposed on the patterned channel layer. Afterwards, a source and a drain are formed on the gate insulating layer by a wet etchant. The part of the hard-mask layer that is not covered by the source and the drain is removed by the wet etchant until the patterned channel layer is exposed, so as to form a plurality of patterned hard-mask layers.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of and claims the priority benefit of a prior application Ser. No. 14/262,802, filed on Apr. 27, 2014, now allowed. The prior application Ser. No. 14/262,802 claims the priority benefit of Taiwan application serial no. 103101470, filed on Jan. 15, 2014. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention generally relates to a transistor and a fabrication method thereof, and more particularly to a transistor having an oxide semiconductor channel layer and a fabrication method thereof.

2. Description of Related Art

Recently, as compared to traditional amorphous silicon (a-Si) thin film transistor, since oxide semiconductor thin film transistor encompasses a higher carrier mobility and a more stable threshold voltage (Vth) while being suitable for large area fabrication, it is widely used in display panels gradually.

In general, there are three types of commonly seen oxide semiconductor thin film transistors (TFTs) including Coplanar TFTs, Island Stop/Etch Stop layer (IS/ESL) TFTs, and Back Channel Etch (BCE) TFTs. Among these, the BCE and IS/ESL type oxide semiconductor thin film transistors have advantages in device characteristics and fabrication yield. Moreover, as compared to IS/ESL TFTs, the BCE TFTs can further save one photolithography and etch process (PEP), and thus has an even better advantage.

However, in the fabrication process of the BCE type oxide semiconductor thin film transistors, a photoresist used for patterning a channel layer would be directly in contact with the channel layer. In addition, the photoresist includes organic solvent which would affect the Subthreshold Swing (SS) of the transistors. As a result, the electrical properties and stability of the transistors are compromised.

SUMMARY OF THE INVENTION

The invention provides a transistor and fabrication method thereof, which can reduce damages in a channel layer thereof.

The invention provides a fabrication method of a transistor which includes the following steps. First, a gate electrode is formed on a substrate. Subsequently, a gate insulating layer is formed on the substrate and the gate electrode to cover the substrate and the gate electrode. Next, a patterned channel layer and a hard-mask layer is formed on the gate insulating layer, the patterned channel layer and the hard-mask layer are located above the gate electrode, and the hard-mask layer is located on the patterned channel layer. Afterwards, a source and a drain are formed on the gate insulating layer by a wet etchant. A part of the hard-mask that is not covered by the source and the drain is removed by the wet etchant until the patterning channel layer is exposed so as to form a plurality of patterned hard-mask layers.

In an embodiment of the invention, the material of the aforementioned patterned hard-mask layer is the same as at least part of the material of the source and the drain.

In an embodiment of the invention, the material of the aforementioned patterned hard-mask layer includes metal or tin-free oxide semiconductor, and the material of the patterned channel layer includes tin-containing oxide semiconductor or poly-Indium-Gallium Oxide (poly-IGO).

In an embodiment of the invention, a sheet resistance of the aforementioned patterned channel layer ranges from 10⁷ ohm/unit area to 10¹⁰ ohm/unit area.

In an embodiment of the invention, the aforementioned patterned hard-mask layer, the source, and the drain are formed through etching by the same etchant.

In an embodiment of the invention, the aforementioned wet etchant includes a mixture containing at least two acids selected from sulfuric acid, phosphoric acid, nitric acid, and acetic acid.

In an embodiment of the invention, the aforementioned wet etchant includes sulfuric acid, phosphoric acid, nitric acid, or acetic acid.

In an embodiment of the invention, the aforementioned method for forming the patterned channel layer and the hard-mask layer on the gate insulating layer including: forming a channel material layer and a hard-mask material layer on the gate insulating layer in sequence; forming a first patterned photoresist layer on the hard-mask material layer and using the first patterned photoresist layer as a mask to remove part of the channel material layer and the hard-mask material that is not covered by the first patterned photoresist layer, thereby fonning the patterned channel layer and the hard-mask layer; and removing the first patterned photoresist layer.

In an embodiment of the invention, the aforementioned method for forming the source, the drain, and the patterned hard-mask layer including: forming a metal material layer on the patterned channel layer and the hard-mask layer; forming a second patterned photoresist layer on the metal material layer and using the second patterned photoresist layer as a mask to remove the metal material layer that is not covered by the second patterned photoresist layer by the wet etchant, thereby forming the source and the drain; and removing the hard-mask layer located between the source and the drain that is not covered by the second patterned photoresist layer by the wet etchant, thereby forming the patterned hard-mask layer.

In an embodiment of the invention, an etching rate of the source and the drain with the wet etchant is V_(SD), an etching rate of the patterned channel layer with the wet etchant is V_(CH), an etching rate of the hard-mask layer with the wet etchant is V_(HM). And V_(SD), V_(CH), and V_(HM) satisfy the following equations:

10≦V _(HM) /V _(CH)≦100; and

0.1≦V _(SD) /V _(HM)≦10.

The invention provides a transistor, which includes a gate electrode, a gate insulating layer, a patterned channel layer, a plurality of patterned hard-mask layers, a source, and a drain. The gate insulating layer covers the gate electrode. The patterned channel layer is disposed on the gate insulating layer and is located above the gate electrode. A sheet resistance of the patterned channel layer ranges from 10⁷ ohm/unit area to 10¹⁰ ohm/unit area. The patterned hard-mask layers are disposed on the patterned channel layer. The source and the drain are disposed on the gate insulating layer, and the patterned hard-mask layers are respectively disposed between the source and the patterned channel layer, and between the drain and the patterned channel layer.

In an embodiment of the invention, the material of the aforementioned patterned hard-mask layer includes tin-free oxide semiconductor, and the material of the patterned channel layer includes tin-containing oxide semiconductor or poly-Indium-Gallium Oxide (poly-IGO).

In an embodiment of the invention, the material of the aforementioned patterned hard-mask layer includes Indium-Gallium Oxide (IGO), Indium-Zinc Oxide (IZO), Indium-Gallium-Zinc Oxide (IGZO), Al-doped ZnO (AZO), Zinc Oxide (ZnO), Indium Oxide (In₂O₃), or Gallium Oxide (Ga₂O₃). The material of the patterned channel layer includes Indium-Tin-Zinc Oxide (ITZO), Zinc-Tin Oxide (ZTO), Zinc-Tin Oxide:Indium (ZTO:In), Zinc-Tin Oxide:Gallium (ZTO:Ga), Indium-Gallium-Zinc Oxide: Stannum (IGZO: Sn), Gallium-Tin Oxide (GTO), Indium-Gallium-Tin Oxide (IGTO), or poly-IGO.

In an embodiment of the invention, the aforementioned patterned hard-mask layer exposes part of the patterned channel layer.

Accordingly, the transistor and the fabrication method thereof provided in the invention can prevent the channel layer to be directly in contact with the photoresist, thereby allowing the transistor to have a better subthreshold swing and stability.

To make the above features and advantages of the invention more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A to FIG. 1G are schematic flow diagrams of the fabrication process of a transistor according to an embodiment of the invention.

FIG. 2 is the etching selectivity of aluminum etchant with respect to molybdenum, IGZO, and ITZO, respectively at 40° C.

FIG. 3A is a characteristic curve diagram of a transistor according to an embodiment of the invention.

FIG. 3B is a characteristic curve diagram of a conventionally known transistor.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1A to FIG. 1G are schematic flow diagrams of the fabrication process of a transistor according to an embodiment of the invention. Referring to FIG. 1A, first, a substrate 100 is provided, and a gate electrode 102 is formed on the substrate 100. In the present embodiment, the substrate 100 is, for example, rigid substrate, flexible substrate, or the like. For instances, rigid substrate can be glass substrate, and flexible substrate can be plastic substrate. In addition, the gate electrode 102 is, for example, single layer or stacked multi-layer metal material, and the metal material is, for example, at least one metal selected from a group consisting of the following metals: copper (Cu), Molybdenum (Mo), Titanium (Ti), Aluminum (Al), Tungsten (W), Silver (Ag), Gold (Au), and alloys thereof. The gate electrode 102 can be fabricated by patterning metal material through lithography.

Referring to FIG. 1B, subsequently, a gate insulating layer 104 is formed on the substrate 100 and the gate electrode 102, and the gate insulating layer 104 covers the substrate 100 and the gate electrode 102 simultaneously. In the present embodiment, gate insulating layer 104 can be single layer structure or stacked multi-layer composite structure, and the material of the gate insulating layer 104 is, for example, silicon nitride, silica, silicon oxynitride, or other suitable dielectric materials.

Referring to FIG. 1C, after completing the fabrication of the gate insulating layer 104, a channel material layer 106′ and a hard-mask material layer 108′ are formed on the gate insulating layer 104. In detail, after the formation of the gate insulating layer 104, the channel material layer 106′, the hard-mask material layer 108′ and a first patterned photoresist layer 110 are formed on the gate insulating layer 104 in sequence.

The channel material layer 106′ covers the gate insulating layer 104, the hard-mask material layer 108′ covers the channel material layer 106′, the first patterned photoresist layer 110 is disposed on partial region of the hard-mask material layer 108′, and the first patterned photoresist layer 110 is located above the gate electrode 102.

Referring to FIG. 1C and FIG. 1D simultaneously, after the formation of the first patterned photoresist layer 110, the first patterned photoresist layer 110 is used as a mask to remove part of the channel material layer 106′ and part of the hard-mask material layer 108′ that is not covered by the first patterned photoresist layer 110 to form a patterned channel layer 106 and a hard-mask layer 108. In the present embodiment, since the patterned channel layer 106 is not directly in contact with the first patterned photoresist layer 110, the organic solvent in the first patterned photoresist layer 110 will not easily cause damage to the patterned channel layer 106.

In an embodiment of the invention, the material of the patterned channel layer 106 can include tin-containing oxide semiconductors or poly-IGO, such as ITZO, ZTO, ZTO:In, ZTO:Ga, IGZO:Sn, GTO, IGTO, or the like. A sheet resistance of the patterned channel layer 106 ranges from 10⁷ ohm/unit area to 10¹⁰ ohm/unit area. In addition, the material of the hard-mask layer 108 can include metal or tin-free oxide semiconductor, such as IGO, IZO, IGZO, AZO, ZnO, In₂O₃, Ga₂O₃, or the like. To simplify the description, explanation below will be based on utilizing ITZO as an example for the material of the patterned channel layer 106 and utilizing IGZO as an example for the material of the hard-mask layer 108, but the invention is not limited thereto.

Referring to FIG. 1E, after completing the fabrication of the patterned channel layer 106 and the hard-mask layer 108, the first patterned photoresist layer 110 covering the hard-mask layer 108 is removed. Subsequently, a metal material layer 112 is formed on the hard-mask layer 108 and the gate insulating layer 104. Afterwards, a second patterned photoresist layer 114 is formed on the metal material layer 112, and the second patterned photoresist layer 114 is used to define the pattern of source and drain (not illustrated) formed in subsequent process. As shown in FIG. 1E, the second patterned photoresist layer 114 is disposed on the metal material layer 112 and corresponds to the space on top of part of the hard-mask layer 108 and part of the gate insulating layer 104. As mentioned above, the metal material layer 112 can be a single layer structure or a stacked multi-layer composite structure, and the material thereof is, for example, metal materials such as Aluminum (Al), Molybdenum (Mo), Silver (Ag), Palladium (Pd), or alloys thereof. The material of the metal material layer 112 can be the same as or different from the material of the gate electrode 102. Molybdenum/Aluminum/Molybdenum (Mo/Al/Mo) is being used as an example for the material of the metal material layer 112 to demonstrate the explanations of the embodiment. It is worth to note that in the present embodiment, the metal material layer 112 is not limited to the stacked layer structure of Molybdenum/Aluminum/Molybdenum (Mo/Al/Mo).

Referring to FIG. 1E and FIG. 1F, after the formation of the second patterned photoresist layer 114, the metal material layer 112 not covered by the second patterned photoresist layer 114 and the hard-mask layer 108 not covered by the second patterned photoresist layer 114 are removed by the wet etchant to complete the fabrication of a source 112 a and a drain 112 b, thereby allowing the hard-mask layer 108 to be further patterned to form patterned hard-mask layers 108 a and 108 b. Herein, as shown in FIG. 1F, the amount of the patterned hard-mask layers 108 a and 108 b are two, but the invention is not limited thereto. Subsequently, as shown in FIG. 1F, the source 112 a and the drain 112 b are covered on the patterned hard-mask layers 108 a, 108 b and part of the gate insulating layer 104. Specifically, in an embodiment of the invention, the patterned hard-mask layers 108 a and 108 b, the source 112 a, and the drain 112 b can be formed through etching by the same wet etchant. The wet etchant is, for example, sulfuric acid, phosphoric acid, nitric acid, acetic acid, or a mixture containing at least two acids of the above compounds. In other embodiment, the wet etchant can also be aluminum etchant. The aluminum etchant is a mixture containing at least phosphoric acid, acetic acid and nitric acid. In other words, when an etching rate of the source 112 a and the drain 112 b with the wet etchant is V_(SD), an etching rate of the patterned channel layer 106 with the wet etchant is V_(CH), and an etching rate of the hard-mask layer 108 with the wet etchant is V_(HM), then V_(SD), V_(CH), and V_(HM) satisfy the following equations:

10≦V _(HM) /V _(CH)≦100; and

0.1≦V _(SD) /V _(HM)≦10.

Referring to FIG. 1F and FIG. 1G simultaneously, after the formation of the source 112 a and the drain 112 b, the second patterned photoresist layer 114 is removed to preliminarily complete the fabrication of the transistor. As shown in FIG. 1G, the transistor of the present embodiment includes the gate electrode 102, the gate insulating layer 104, the patterned channel layer 106, the patterned hard-mask layers 108 a and 108 b, a source 112 a, and a drain 112 b. The gate insulating layer 104 covers the gate electrode 102. The patterned channel layer 106 is disposed on the gate insulating layer 104 and is located above the gate electrode 102. The sheet resistance of the patterned channel layer 106 ranges from 10⁷ ohm/unit area to 10¹⁰ ohm/unit area. The patterned hard-mask layers 108 a and 108 b are disposed on the patterned channel layer 106. The source 112 a and the drain 112 b are disposed on the gate insulating layer 104, and the patterned hard-mask layers 108 a and 108 b are located between the source 112 a and the patterned channel layer 106 and between the drain 112 b and the patterned channel layer 106.

FIG. 2 is the etching selectivity of aluminum etchant with respect to molybdenum, IGZO, and ITZO, respectively at 40° C. . Referring to FIG. 1E, FIG. 1F, and FIG. 2 simultaneously, under the circumstance of 40° C., the etching rate of Mo with aluminum etchant is V1, the etching rate of IGZO with aluminum etchant is V2, the etching rate of ITZO with aluminum etchant is V3, and V1:V2:V3 is 1:0.1:0.001. In other words, when the material of the source 112 a and the drain 112 b is Mo/Al/Mo, the material of the hard-mask layer 108 is IGZO, and the material of the patterned channel layer 106 is ITZO, the aluminum etchant can effectively etch the metal material layer 112 and the hard-mask layer 108 to form the source 112 a, the drain 112 b, and the patterned hard-mask layers 108 a, 108 b while not excessively damage the patterned channel layer 106.

For example, when the hard-mask layer 108 is formed of a thickness of 10-40 nm, the metal material layer 112 is formed of a thickness of 400-500 nm, then the part of the hard-mask layer 108 not covered by the second patterned photoresist layer 114 (namely, the part of the hard-mask layer 108 not covered by the aforementioned source 112 a and the drain 112 b) will be removed until the patterned channel layer 106 is exposed. That is, the hard-mask layer 108 exposes part of the patterned channel layer 106, and the hard-mask layer 108 is being etched to form two separate parts of patterned hard-mask layers 108 a and 108 b. At this time, after removing the second patterned photoresist layer 114, a transistor structure is obtained, as shown in FIG. 1G.

Moreover, in another embodiment of the invention, the material of the hard-mask layer 108 is the same as at least part of the material of the source 112 a and the drain 112 b, and the examples are metal materials such as Al, Mo, Ag, Pd, or alloys thereof. As mentioned above, the hard-mask layer 108, the source 112 a, and the drain 112 b can be formed through etching by the same etchant, and the details may not be repeated herein.

FIG. 3A is a characteristic curve diagram of a transistor according to an embodiment of the invention. The material of the patterned channel layer of the transistor according to the invention is ITZO, and the material of the patterned hard-mask layer is IGZO. FIG. 3B is a characteristic curve diagram of a conventionally known transistor. The material of the patterned channel layer of the conventionally known transistor is ITZO, but the conventionally known transistor does not include a patterned hard-mask layer. Referring to FIG. 3A and FIG. 3B, a drain-source voltage of 0.1V or 10V is applied between the source and the drain, and the drain current corresponding to the change in gate-source voltage from −20V to +20V is measured. The diagrams are drawn such that the y-axis represents the drain current (Id) of the transistor while the x-axis represents the gate-source voltage (Vgs) of the transistor. Herein, the values of subthreshold swing (S.S.), the threshold voltage (Vt), and the field-effect mobility (Ufe) of the transistor according to an embodiment of the invention and the conventionally known transistor are extracted and presented in the following Table 1:

TABLE 1 Subthreshold Threshold Voltage Field-Effect Swing (S.S.) (Vt) Mobility (Ufe) Transistor of the 0.26 −0.75 25.7 invention Conventionally 0.83 −2.67 26.7 known transistor Unit: Volts

Referring to Table 1, the value of subthreshold swing and threshold voltage of the transistor according to the invention are smaller than that of the conventionally known transistor while the field-effect mobility is hardly being affected. In other words, since the patterned channel layer of the transistor according to the invention is not directly in contact with the patterned photoresist layer, the organic solvent in the patterned photoresist layer will not easily cause damage to the patterned channel layer. Therefore, as compared to the conventionally known transistor, the transistor according to the invention can encompass better parameters values of subthreshold swing and threshold voltage while the field-effect mobility is hardly being affected.

Accordingly, the transistor and the fabrication method thereof provided in the invention can prevent the channel layer to be directly in contact with the photoresist, thereby allowing the transistor to have a better subthreshold swing and threshold voltage.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of the invention provided they fall within the scope of the following claims and their equivalents. 

What is claimed is:
 1. A transistor, comprising: a gate electrode; a gate insulating layer covering the gate electrode; a patterned channel layer, disposed on the gate insulating layer and is located above the gate electrode; a plurality of patterned hard-mask layers, disposed on the patterned channel layer, wherein a part of the patterned channel layer is not covered by the patterned hard-mask layers; and a source and a drain, located on the gate insulating layer, wherein the patterned hard-mask layers are respectively disposed between the source and the patterned channel layer and between the drain and the patterned channel layer, and a material of the patterned hard-mask layers is the same as at least part of a material of the source and the drain.
 2. The transistor according to claim 1, wherein the material of the patterned hard-mask layers comprise tin-free oxide semiconductor, and the material of the patterned channel layer comprises tin-containing oxide semiconductor or poly-Indium-Gallium Oxide (poly-IGO).
 3. The transistor according to claim 1, wherein the material of the patterned hard-mask layers comprise IGO, IZO, IGZO, AZO, ZnO, In₂O₃, or Ga₂O₃, and the material of the patterned channel layer comprises ITZO, ZTO, ZTO:In, ZTO:Ga, IGZO:Sn, GTO, IGTO, or poly-Indium-Gallium Oxide (poly-IGO).
 4. The transistor according to claim 1, wherein a sheet resistance of the patterned channel layer ranges from 10⁷ ohm/unit area to 10¹⁰ ohm/unit area. 